The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a pixel array of the CMOS image sensor in a wider dynamic range.
Generally, an image sensor is an apparatus to capture images using light sensing semiconductor materials. Since brightness and wavelength of light from an object are different in their amount according to the reflection area, electrical signals from pixels are different from one another. These electrical signals are converted into digital signals, which can be processed in a digital circuit, by an analogue-to-digital converter. Thus, the image sensor needs a pixel array having tens to hundreds of thousands of pixels, a converter for converting analogue voltages into digital voltages, hundreds to thousands of storage devices and so on.
Referring to FIG. 1, a conventional CMOS image sensor includes a control and interface unit 10, a pixel array 20 having a plurality of CMOS image sensing elements, and a single slope AD converter 30. The single slope AD converter 30 also includes a ramp voltage generator 31 for generating a reference voltage, a comparator (operational amplifier) 32 for comparing the ramp voltage with an analogue signal from the pixel array 20 and a double buffer 40.
The control and interface unit 10 controls the CMOS image sensor by controlling an integration time, scan addresses, operation modes, a frame rate, a bank and a clock division and acts as an interface with an external system. The pixel array 20 consisting of Nxc3x97M unit pixels having excellent light sensitivity senses images from an object. Each pixel in the pixel array 20 includes a transfer transistor, a reset transistor and a select transistor. The single slope AD converter 30 converts analogue signals from the pixel array 20 into digital signals. This AD conversion is carried out by comparing the ramp voltage with the analogue signals. The comparator 32 searches for a point at which the analogue signals are the same as the falling ramp voltage with a predetermined slope. When the ramp voltage is generated and then starts falling, the control and interface unit 10 generates count signals to count the degree of the voltage drop. For example, the ramp voltage starting the voltage drop, the converted digital value may be xe2x80x9c20xe2x80x9d in the case where the analogue signals are the same as the falling ramp voltage at 20 clocks of the control and interface unit 10. This converted digital value is stored in the double buffer 40 as digital data.
FIG. 2 is a circuit diagram illustrating a conventional unit pixel. Referring to FIG. 2, where the CMOS image sensor is based on the correlated double sampling (hereinafter, referred to as a CDS) for high quality images, a unit pixel 100 in the pixel array includes a photodiode and four transistors. In other words, the unit pixel 100 includes a transfer transistor MT, a reset transistor MR, a drive transistor MD and a select transistor MS. The transfer transistor MT transfers photoelectric charges generated in the photodiode 101 to sensing node D, the reset transistor MR resets sensing node D in order to sense a next signal, the drive transistor MD acts as a source follower and the select transistor MS outputs the digital data to an output terminal in response to the address signals.
In accordance with the CDS, the unit pixel 100 obtains a voltage corresponding to a reset level by turning on the reset transistor MR and turning off the transfer transistor MT. Also, the unit pixel 100 obtains a data level voltage by turning off the transfer transistor MT in a turned-off state of the reset transistor MR and reading out photoelectric charges generated in the photodiode 101. An offset, which is caused by the unit pixel 100 and the comparator 32, may be removed by subtracting the data level from the reset level. This removal of the offset is essential to the CDS. That is, by removing an unexpected voltage in the unit pixel 100, it is possible to obtain a net image data value. At this time, a clock coupling is generated by a parasitic capacitor of the transfer transistor MT, the reset transistor MR and the drive transfer transistor MD according to repetitively turning on and off of the transfer and reset transistors MT and MR.
FIG. 3 shows a timing chart illustrating control signals applied to the transistors of the unit pixel shown in FIG. 2. The operation of the unit pixel 100 will be described with reference to FIG. 3.
1) In section xe2x80x9cAxe2x80x9d, the transfer transistor MT and the reset transistor MR are turned on and the select transistor MS is turned off, so that the photodiode 101 is fully depleted.
2) In section xe2x80x9cBxe2x80x9d, the reset transistor MR keeps on a turned-on state and the transfer transistor MT is turned off so that a reset voltage level is transferred through the reset transistor MR to a sensing node D, and then the select transistor MS is turned on so that the reset voltage level is outputted through the select transistor MS to an output terminal (a reset voltage level).
3) In section xe2x80x9cCxe2x80x9d, the select transistor MS and the transfer transistor MT are turned off and turned on, respectively, thus the unit pixel 100 reads out photoelectric charges generated in the photodiode 101. Then, the select transistor MS is turned on again so that a data voltage level is outputted to the output terminal (a data voltage level).
Here, the drive transistor MD acts as a source follower so that the output signal is determined by the charges, that is, the amount of charges generated in the photodiode 101 and it is outputted to the output terminal while the select transistor MS is turned on. At this moment, the final output of the unit pixel 100 is determined by a biasing signal Bias applied to a load transistor MB. As a result, the biasing signal Bias has an effect on the potential of the sensing node D, that is, the gate-source voltage of the drive transistor MD. Such an effect results in reducing the gate-source voltage, i.e., a dynamic range. Referring again to FIG. 2, the potential of the sensing node D is approximately 2.6V during the reset voltage level (in the above section xe2x80x9cAxe2x80x9d) and approximately 1.7V during the data voltage level (in the above section xe2x80x9cBxe2x80x9d), so that the CMOS image sensor is in a dynamic range of approximately 0.9V and the CMOS image sensor outputs the data based on the variation of gate-source voltage of source follower. Accordingly, the operation of the unit pixel 100 may apply to that of another unit pixels.
Thus, there is a problem that the variation of voltage in the output terminal is in a narrow range, which deteriorates the quality of picture in the CMOS image sensor.
It is, therefore, an object of the present invention to provide a CMOS image sensor that is based on CDS and provides a unit pixel array with a wider dynamic range.
In accordance with an aspect of the present invention, there is provided a CDS-based CMOS image sensor, comprising: a) a single common node; b) a plurality of unit pixels in parallel connected to the single common node; c) an amplifying means coupled to the single common node for amplifying a voltage of the single common node and outputting the amplified voltage; d) an output means for receiving the amplified voltage from the amplifying means and outputting a data voltage level and a reset voltage level.